Teaching
Textbook: Industry Chip Design Flow
X. Yang, Integrated Circuit Design: IC Design Flow and Project-Based Learning, 1st edition. Boca Raton: CRC Press, 2024. DOI: 10.1201/9781003187080. ISBN: 978-1-032-03079-1. 506 pages.
Please find the open materials to the textbook.
📄 Lec1; 📄 Lec2; 📄 Lec3; 📄 Lec4; 📄 Lec5; 📄 Lec6; 📄 Lec7; 📄 Lec8; 📄 Lec9; 📄 Lec10; 📄 Lec11; 📄 Lec12
Teaching Experience
- Master’s Thesis (CENG 6939)
- Research Project and Seminar (CENG 6838)
- Integrated Circuit Design Flow (CENG 5931 / CENG 4931)
- Graduate Independent Study (CENG 5919)
- Advanced Digital System Design (CENG 5534)
- Undergraduate Independent Study (CENG 4389)
- Digital System Design (CENG 4354)
- Senior Project I & II (CENG 4265 / CENG 4266)
- Electronics (CENG 3316) 📄 Lec1; 📄 Lec2; 📄 Lec4; 📄 Lec5; 📄 Lec6; 📄 Lec7; 📄 Lec14;
- Lab for Computer Architecture (CENG 3151)
- Lab for Electronics (CENG 3116)
- Lab for Linear Circuits (CENG 2113)
- Lab for Digital Circuits (CENG 2112)
Industry Experience
- AMD — Senior IC Design and Verification Engineer (2011–2012)
- Assertion tool development and testing
- UVM verification methodology
- USB 3.0 and PCIe design and research
- Low-power design and verification, including clock gating and power-domain description
- IP design and verification: I2C, SPI, GPIO, SDIO, UART, Flash, Smart Card, IR, interrupt handler, semaphore
- DMA and DDR controller design and verification
- CEC HED Corp. — Senior IC Verification Engineer (2009–2010)
- IEEE 802.11a/b/g/n system-level verification
- UVM methodology and RGM (Register and Memory Package)
- Low-power design
- Mixed-signal verification using RVM (Real-Valued Modeling)
- DA, DeMux, and Delta-Sigma modulator design
- IEEE 802.11a/b/g/n baseband (BBP) verification
- Constraint random verification, functional and code coverage, assertion design
- Transmit, receive, and signal channel model integration
- RF model design using RVM: LNA, mixer, VGA, ADC, PA, DAC
- IEEE 802.11a/b/g/n system-level verification
- PowerLayer MicroSystems Corp. (PLM) — IC Design Engineer (2007–2008)
- USB 2.0 OTG integration and verification
- USB 2.0 host, Synopsys Nano-PHY, and VIP integration and verification
- USB 2.0 and UTMI+ integration
- Ethernet integration and verification
- Synopsys MII / RMII PHY integration
- 10/100 Mbps data, full-duplex, IEEE 802.3x support
- SoC bus integration and verification
- PLM3K circuit system-level verification
- V3K CPU design and verification
- SoC peripherals: I2C, SPI, GPIO, SDIO, UART, Flash controller, Smart Card controller, IR controller
- Post-processing verification: TNR, SNR, scaler, SE plane
- USB 2.0 OTG integration and verification
Methodologies, Languages, and EDA Tools
- Professional experience in ASIC / FPGA / SoC industrial design flows
- Hardware description languages: Verilog, VHDL
- Hardware verification language: SystemVerilog
- Design and verification scripting: dj, dv, Tcl, C shell, Makefile, Perl
- Verification methodologies: ADV, CDV, CRV
- UNIX / Linux environments and EDA tools: Vim, Debussy / Verdi, ModelSim / Questa, NC, VCS, DC, PrimeTime
- FPGA tools: Xilinx ISE and Vivado, Intel Quartus
- Verification methodologies: VMM and UVM
- Low-power design techniques: clock gating and power-domain design (CPF, UPF)
- Mixed-signal verification familiarity: SPICE, AMS, RVM
Industrial Specifications
- SoC architectures: AMBA APB, AHB, AXI, OCP, Wishbone
- SoC controllers: ARM, MIPS, DMA, DDR2 controller
- Security protocols: AES, DES
- Interface specifications: USB 2.0 OTG (Nano-PHY, VIP, UTMI+), IEEE 802.3x Ethernet (MII / RMII PHY), PCIe, infrared remote
- Wireless communication protocols: Wi-Fi 802.11a/b/g/n baseband, Bluetooth 4.0 (LE)
- SoC peripherals: interrupt controller, semaphore, UART, I2C, SPI, SDIO, GPIO, watchdog, timer
- Memory controllers: Smart Card, NAND / NOR / serial flash, EEPROM
- Graphics and video modules: TNR, SNR, scaler, SE, pre-processing, post-processing
- Mixed-signal model design familiarity: DAC, DeMux, Delta-Sigma modulator, LNA, mixer, VGA, ADC, PA