Xiaokun (Bobbie) Yang

Xiaokun (Bobbie) Yang

Professor, UHCL
Affiliate Faculty, LBNL

Publications

Book

Patents

  1. Xiaokun Yang, Shuai Xu, Vipin Chaudhary, and Xuechen Zhang. “Accelerated Mixed-Precision Quantum Circuit Simulation with Automated Hardware Generation,” U.S. Patent, Filed by University of Houston System, 2026.
  2. Shuai Xu, Vipin Chaudhary, and Xiaokun Yang. “Scaling quantum circuit simulation through the integration of circuit cutting and hardware acceleration,” U.S. Patent, Pending, 2026.
  3. X. Yang and J. Andrian, “An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems,” U.S. Patent US20170302438A1, October 19, 2017.
  4. X. Yang, “A Mixed-Signal Verification System for Sigma-Delta Filters,” China Patent CN102955871A, 2013.
  5. W. Teng, J. Sun, L. Mo, J. Zou, Y. Wu, F. Liao, J. Zhang, X. Yang, and D. Li, “Method and Device for Detecting Frame Signals of Wireless Local Area Network (WLAN) Equipment,” China Patent CN102970688A, 2013.

Released IPs

Journals

  1. [TCAD 2027] Xiaokun Yang, Spencer Miles Buchanan, Dania Susanne Mosuli, Blair Reasoner, Meriam Gay Bautista-Jurney, Doru Adrian Thom Popovici, and John Shalf, “GenTSQR: A Parameterized Hardware Generator for Streaming and Spatially Parallel QR Factorization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Submitted, 2026.
  2. [ToE 2025] X. Yang* and X. Zhang, “Bridging Chip Design and Machine Learning in Undergraduate Digital Systems Curriculum,” IEEE Transactions on Education. Major revision, 2025.
  3. [Micromachines 2023] Mukesh Chowdary Madineni, Mario Vega, and X. Yang, “Parameterizable Design on Convolutional Neuron Networks with Chisel Hardware Construction Language,” Micromachines 2023, 14(3), 531; Paper
  4. [ToE 2021] X. Yang*, “Bridging the Gap Between Academia and Industry Needs with an Open-Source Platform in Teaching Digital System Design,” IEEE Transactions on Education, Vol. 64, No. 4, pp. 337–344, November 2021. Paper.
  5. [JSC 2021] I. Westby and X. Yang*, “FPGA Acceleration on a Multi-Layer Perceptron Neural Network for Digit Recognition,” The Journal of Supercomputing, Springer, pp. 1–18, May 2021. Paper.
  6. [JCSC 2021] X. Yang* and S. Shi, “Exploiting Energy–Quality Tradeoffs on Approximate FPGA Designs of Scalable Sequential Circuits,” Journal of Circuits, Systems and Computers, Vol. 30, No. 4, Article 2150062, August 2021. Paper.
  7. [NNW 2020] H. He, X. Yang*, et al., “Iterated Dilated Convolutional Neural Networks for Word Segmentation,” Neural Network World, Vol. 30, No. 5, pp. 333–346, October 2020. Paper.
  8. [IET-CDT 2020] X. Yang*, S. Sha, I. Unwala, and J. Lu, “Towards Third-Party IP Integration: A Case Study of High-Throughput and Low-Cost Wrapper Design on a Novel IBUS Protocol,” IET Computers & Digital Techniques, Vol. 14, No. 6, pp. 353–362, November 2020. Paper.
  9. [TODAES 2019] S. Sha, A. S. Bankar, X. Yang, W. Wen, and G. Quan, “On Fundamental Principles for Thermal-Aware Design on Periodic Real-Time Multi-Core Systems,” ACM Transactions on Design Automation of Electronic Systems, Vol. 25, No. 2, February 2020. Paper.
  10. [JoC 2019] X. Yang*, et al., “A Vision of Fog Systems Integrating FPGAs and BLE Mesh Networks,” Journal of Communications, Vol. 14, No. 3, pp. 210–215, March 2019.
  11. [JETC 2018] X. Yang*, W. Wen, and M. Fan, “Improving AES Core Performance via an Advanced IBUS Protocol,” ACM Journal on Emerging Technologies in Computing, Vol. 14, No. 1, pp. 1–23, March 2018. Paper.
  12. [IJCA 2018] Y. Zhang, X. Yang*, et al., “Hierarchical Synthesis of Approximate Multiplier Design for Field-Programmable Gate Arrays,” International Journal of Computer Applications, Vol. 180, No. 17, pp. 1–7, February 2018.
  13. [VLSID 2017] X. Yang*, N. Wu, and J. Andrian, “Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure,” Journal of VLSI Design, Article ID 4914301, pp. 1–7, May 2017. Paper.
  14. [JSS 2017] M. Fan, Q. Han, and X. Yang, “Energy Minimization for Online Real-Time Scheduling with Reliability Awareness,” Journal of Systems and Software, Vol. 127, pp. 168–176, May 2017. Paper.
  15. [IJCA 2017] J. Thota, P. Vangali, and X. Yang*, “Prototyping an Autonomous Eye-Controlled System Using Raspberry Pi for Wheelchairs,” International Journal of Computer Applications, Vol. 158, No. 8, pp. 1–7, January 2017.
  16. [CAE 2017] P. Vangali and X. Yang*, “A Compression Algorithm Design and Simulation for Processing Large Volumes of Data from Wireless Sensor Networks,” Communications on Applied Electronics, Vol. 7, No. 4, pp. 1–5, June 2017.
  17. [Integration 2016] X. Yang*, N. Wu, and J. Andrian, “A Novel Bus Transfer Mode: Block Transfer and a Performance Evaluation Methodology,” Integration, the VLSI Journal, Vol. 52, pp. 23–33, January 2016. Paper
  18. [IJDKP 2016] K. Zeng, N. Wu, X. Yang, and K. K. Yen, “FHCC: A Soft Hierarchical Clustering Approach for Collaborative Filtering Recommendation,” International Journal of Data Mining & Knowledge Management Process, Vol. 6, No. 3, May 2016.
  19. [TVLSI 2015] X. Yang* and J. Andrian, “A High-Performance On-Chip Bus (MSBUS) Design and Verification,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 23, No. 7, pp. 1350–1354, July 2015. Paper

Conferences

  1. [FPGA 2027] Muhammad Athar Waqas, Dania Susanne Mosuli, Spencer Miles Buchanan, Doru Adrian Thom Popovici, John Shalf, and Xiaokun Yang “GenStencil: An Architecture-Aware Hardware Generator for Scalable Stencil Acceleration on Multi-SLR FPGAs”, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (ISFPGA’27), Submitted, March 14 – March 16, 2027, San Francisco, CA, USA.
  2. [ISQED 2027] Xiaokun Yang, Jeremy W. Turner, Cameron D. Disomma, Yunhe Feng, Xinpeng Li, Shuai Xu, Vipin Chaudhary and Xuechen Zhang. “Precision-Configurable Hardware Generation for FPGA-Based Quantum Circuit Simulation and Acceleration”, 28th International Symposium on Quality Electronic Design (ISQED’27), Submitted, April 14-16, 2027, San Francisco, CA, USA.
  3. [BigData-REU 2026] Krishna Patel, Sumera Anjum, Spencer Buchanan, Xuechen Zhang, Yunhe Feng, and Xiaokun Yang, “Evaluating LLM-Generated Hardware for Quantum Circuit Simulation”, International Conference on Big Data, Submitted, Dec 14-17, 2026, Phoenix, Arizona, USA
  4. [BigData-REU 2026] Spencer Miles Buchanan, Dania Susanne Mosuli, Muhammad Athar Waqas, Mario Vega, Xuechen Zhang, and Xiaokun Yang, “Hierarchical Hardware Generation for Floating-Point Kernels: A Comparison of Chisel and LLM-Based Approaches”, International Conference on Big Data, Submitted, Dec 14-17, 2026, Phoenix, Arizona, USA
  5. [QAI 2026] Sumera Anjum, Xiaokun Yang, Thomas Gerrity, Junhua Ding, Kewei Sha, Weijian Zheng, Song Fu and Yunhe Feng, “Beyond Vibe Coding: Unified Multi-Framework Quantum Code Generation and Execution-Aware Evaluation with LLMs”, 2026 IEEE 2nd International Conference on Quantum Artificial Intelligence (QAI-2026), Accepted, 13-16 December 2026, Nottingham, UK.
  6. [QCE 2026] Qingwen Liu, Xinpeng Li, Ji Liu, Xiaokun Yang, Lauren Li, Yifan Yu, Yang Zhang, Liran Ma, Shuai Xu and Vipin Chaudhary, “Non-Separable Wire Cutting: Enhancing Quantum Compilation”, IEEE Quantum Week, Accepted, 13 - 18 September 2026, Metro Toronto Convention Centre Toronto, Ontario, Canada.
  7. [HPDC 2026] Xiaokun Yang, Xinpeng Li, Jeremy W Turner, Cameron D Disomma, Yunhe Feng, Xuechen Zhang, Vipin Chaudhary, and Shuai Xu. 2026. Scalable Quantum Circuit Simulation via Circuit Cutting and FPGA Acceleration. In Proceedings of the 35th International Symposium on High-Performance Parallel and Distributed Computing (HPDC ‘26), QUASAR Workshop. Association for Computing Machinery, New York, NY, USA, 642–650. July 13, 2026. Paper
  8. [CCGrid 2026] Simon Zhang, Shuai Xu, Zhengxiong Li, Fangtian Zhong, Xiaokun Yang, and Hailu Xu “SwiftBot: A Decentralized Platform for LLM-Powered Federated Robotic Task Execution” The 26th IEEE International Symposium on Cluster, Cloud, and Internet Computing (CCGrid 2026, Acceptance rate: 25%), 18–21 May 2026, Sydney, Australia. Paper
  9. [IMNS 2026] B. Mikailenko, R. Rongon, X. Yang and X. Zhang, “MemMax: Memory-Parallel FPGA Optimization for Bandwidth-Bound IoT Image Processing,” 2026 International Conference on Intelligent Multimedia, Networking, and Security (IMNS), Atlanta, GA, USA, 2026, pp. 1-6, Paper
  10. [DCAS 2026] Y. Feng, X. Yang, K. Sha and J. Ding, “Benchmarking the Benchmarks for Quantum Code Generation with LLMs,” 2026 IEEE 19th Dallas Circuits and Systems Conference (DCAS), Dallas, TX, USA, 2026, pp. 1-4, Paper.
  11. [FML 2026] Angelos Ioannou, Fabien Chaix, Doru Thom Popovici, Mario Vega, Tan Nguyen, Giuseppe Di Guglielmo, Benjamin Hawks, Aaron Young, Xiaokun Yang, Dania Mosuli, Nhan Tran, and John Shalf, “STRIDE: An Automated Design Space Exploration Workflow for Generating AI Training Datasets from Hierarchical Mathematical Kernels”, The Fast Machine Learning for Science Conference 2026, August 31- Sept. 4, 2026, Sand Diego, USA.
  12. [FPGA 2026] Doru Thom Popovici, Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, and John Shalf. 2026. A Hierarchical Methodology for Hardware Design Comparison in HPC Workloads. In Proceedings of the 2026 ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA ‘26). February 21, 26, Association for Computing Machinery, New York, NY, USA. Paper
  13. [DCAS 2026] Yunhe Feng, Xiaokun Yang, Kewei Sha, Junhua Ding, “Benchmarking the Benchmarks for Quantum Code Generation with LLMs”, 2026 19th IEEE Dallas Circuits and Systems Conference, Accepted, April 10 to 12, 2026, Dallas, TX, USA.
  14. [FPGA 2025] Doru Thom Popovici and Mario Vega and Angelos Ioannou and Fabien Chaix and Dania Mosuli and Blair Reasoner and Tan Nguyen and Xiaokun Yang and John Shalf, “Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads,” arXiv preprint arXiv:2509.09774, 2025. Paper
  15. [ICDM-REU 2025] S. M. Buchanan, J. Ramos, C. D. DiSomma, Y. Zhang, W. Zhao and X. Yang, “Parameterized Hardware Generation for Mini-Float Summation-of-Absolute-Differences for AdderNet Based CNN Models,” 2025 IEEE International Conference on Data Mining Workshops (ICDMW), Washington, DC, USA, 2025, pp. 2780-2785, Paper.
  16. [ICDM-REU 2025] J. W. Turner, C. D. DiSomma, X. Zhang, L. Fan and X. Yang, “Hardware Generation for Quantum Gate Emulation and Acceleration,” 2025 IEEE International Conference on Data Mining Workshops (ICDMW), Washington, DC, USA, 2025, pp. 1-6, Paper.
  17. [ICDM-REU 2025] K. Powell, R. Rongon, X. Yang and X. Zhang, “Accelerating Deep-Learning Applications with Efficient Tensor Layout Management,” 2025 IEEE International Conference on Data Mining Workshops (ICDMW), Washington, DC, USA, 2025, pp. 1-6, Paper.
  18. [SEET 2025] DiSomma, C.D., Mosuli, D.S., Xu, H., Yang, X. (2026). A Scalable Software-Hardware Co-design FPGA Platform for Floating-Point Operations. In: Hussain, S., Khan, A.A., Abdul Basit Ur Rahim, M., Khan, S.U.R. (eds) SEET—Software Engineering for Emerging Technologies. SEET 2025. Communications in Computer and Information Science, vol 2725. Springer, Cham.
  19. [SEET 2025] Cruz, A., Wu, Y., Yang, X. (2026). AI-Powered Engine Component Identifier for Vehicle Maintenance. In: Hussain, S., Khan, A.A., Abdul Basit Ur Rahim, M., Khan, S.U.R. (eds) SEET—Software Engineering for Emerging Technologies. SEET 2025. Communications in Computer and Information Science, vol 2725. Springer, Cham.
  20. [AIIoT 2025] N. Wu, B. Fong, X. Yang and K. Zeng, “Hardware-Accelerated Music Transcription on the Cloud via FPGA Implementation,” 2025 IEEE World AI IoT Congress (AIIoT), Seattle, WA, USA, 2025, pp. 0299-0308, Paper.
  21. [BigData 2024] Paul Wong, Dania Susanne Mosuli, Xuechen Zhang, and Xiaokun Yang, “Hardware Generation on Trigonometric Functions,” 2024 IEEE Big Data, DC, USA, 2024, pp. 7571–7576, Paper.
  22. [HPEC 2023] Mario Vega, X. Yang, John Shalf, and Doru Adrian Thom Popovici, “Towards a Flexible Hardware Implementation for Mixed-Radix Fourier Transforms,” 2023 IEEE High Performance Extreme Computing Conference (HPEC), Boston, MA, USA, 2023, pp. 1–7, Paper.
  23. [UEMCON 2023] C. Hingu, X. Fu, R. Challoo, J. Lu, X. Yang, and L. Qingge, “Accelerating FPGA Implementation of Neural Network Controllers via 32-bit Fixed-Point Design for Real-Time Control,” 2023 IEEE 14th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), Best Paper Award, New York, NY, USA, 2023, pp. 0445–0450, doi: Paper.
  24. [CLOUD 2022] G. Ding, Z. Li, Y. Wu, X. Yang, M. Aliasgari, and H. Xu, “Towards an Efficient Client Selection System for Federated Learning,” in Ye, K., Zhang, LJ. (eds) Cloud Computing (CLOUD 2022). Lecture Notes in Computer Science, Vol. 13731. Springer, Cham.
  25. [DAC 2022] S. Sha and X. Yang, “Endurance Aware Real Time Scheduling on ReRAM Accelerators,” IEEE/ACM 2022 Design Automation Conference (DAC 2022), WIP, Moscone West, San Francisco, USA, 2022.
  26. [ISQED 2022] A. L. Reed and X. Yang, “Lightweight Neural Network Architectures for Resource-Limited Devices,” IEEE/ACM 23rd International Symposium on Quality Electronic Design (ISQED 2022, Acceptance Rate: 30%), pp. 1–7, Santa Clara, CA, USA, 2022. Paper
  27. [ISMCR 2022] M. Vega, M. Madineni, and X. Yang, “Case Studies of Configurable Binary Design Library on FPGA,” IEEE 23rd International Symposium on Measurement and Control in Robotics (ISMCR 2022), pp. 1–5, Houston, TX, USA, 2022.
  28. [ISMCR 2022] S. K. Surapally and X. Yang, “Evaluating FPGA Acceleration on Binarized Neural Networks and Quantized Neural Networks,” IEEE 23rd International Symposium on Measurement and Control in Robotics (ISMCR 2022), pp. 1–5, Houston, TX, USA, 2022.
  29. [GreenTech 2022] M. Ejaz, I. Unwala, J. Lu, and X. Yang, “Securing Hardware Development Process using Blockchain,” 2022 IEEE Green Technologies Conference (GreenTech), pp. 150–153, Houston, TX, USA, 2022.
  30. [CSCE 2021] S. Ek, M. Curci, X. Yang, et al., “Sentiment Analysis of Long-term Social Data during the COVID-19 Pandemic,” The 2020 World Congress in Computer Science, Computer Engineering, and Applied Computing (CSCE 2020), Las Vegas, 2021.
  31. [ICAI 2021] I. Westby, H. Koc, J. Lu, and X. Yang, “A Design on Multilayer Perceptron (MLP) Neural Network for Digit Recognition,” pp. 729–741, Advances in Artificial Intelligence and Applied Cognitive Computing. Transactions on Computational Science and Computational Intelligence. Springer, Cham, 2020.
  32. [ICAI 2021] A. Gajjar, S. Dave, T. Andrew Yang, L. Wu, and X. Yang, “An IoT-Edge-Server System with BLE Mesh Network, LBPH, and Deep Metric Learning,” pp. 757–773, Advances in Artificial Intelligence and Applied Cognitive Computing. Transactions on Computational Science and Computational Intelligence. Springer, Cham, 2021.
  33. [ICAI 2021] X. Yang, T. Andrew Yang, and L. Wu, “An Edge Detection IP of Low-cost System-on-Chip for Autonomous Vehicles,” pp. 775–786, Advances in Artificial Intelligence and Applied Cognitive Computing. Transactions on Computational Science and Computational Intelligence. Springer, Cham, 2021.
  34. [CSCE 2021] L. Wu, A. Yang, A. Dubrovskiy, H. He, H. Yan, X. Yang, et al., “Advancing AI-aided Computational Thinking in STEAM (Science, Technology, Engineering, Arts, Math) Education (Act-STEAM),” pp. 787–795, Advances in Artificial Intelligence and Applied Cognitive Computing. Transactions on Computational Science and Computational Intelligence. Springer, Cham, 2020.
  35. [CSCE 2021] L. Wu, A. Yang, H. Yan, X. Yang, et al., “Realistic Drawing & Painting with AI Supported Geometrical and Computational Method (Fun-Joy),” pp. 797–804, Advances in Artificial Intelligence and Applied Cognitive Computing. Transactions on Computational Science and Computational Intelligence. Springer, Cham, 2020.
  36. [ISQED 2019] X. Yang, Y. Zhang, and L. Wu, “A Scalable Image/Video Processing Platform with Open Source Design and Verification Environment,” 20th International Symposium on Quality Electronic Design (ISQED 2019, Acceptance Rate: 35%), pp. 110–116, Santa Clara, CA, USA, 2019. Paper
  37. [ISVLSI 2019] K. Vaca, A. Gajjar, and X. Yang, “Real-Time Automatic Music Transcription (AMT) with Zync FPGA,” 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2019, Acceptance Rate: 17%), pp. 378–384, Miami, FL, USA, 2019. Paper
  38. [ISVLSI 2019] Y. Zhang and X. Yang, “A Case Study On Approximate FPGA Design With an Open-Source Image Processing Platform,” 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2019, Acceptance Rate: 17%), pp. 372–377, Miami, FL, USA, 2019. Paper
  39. [ISMCR 2019] K. Vaca, M. Jefferies, and X. Yang, “An Open Real-Time Audio Processing Platform on Zync FPGA,” International Symposium on Measurement and Control in Robotics (ISMCR 2019), pp. D1-2-1–D1-2-6, Houston, TX, USA, 2019.
  40. [ISMCR 2019] X. Zhang, J. Lu, X. Fu, X. Yang, I. Unwala, and T. Zhang, “Tracking of Targets in Mobile Robots Based on Camshift algorithm,” International Symposium on Measurement and Control in Robotics (ISMCR 2019), pp. B2-3-1–B2-3-5, UHCL, Houston, USA, Sept 19–21, 2019.
  41. [ICAI 2019] H. He, L. Wu, H. Yan, and X. Yang, “Synthesize Corpus for Chinese Word Segmentation,” The 21st International Conference on Artificial Intelligence (ICAI 2019), pp. 129–134, Las Vegas, NV, USA, 2019.
  42. [HONET-ICT 2019] J. Gopaluni, I. Unwala, J. Lu, and X. Yang, “Graphical User Interface for OpenThread,” 2019 IEEE 16th International Conference on Smart Cities: Improving Quality of Life Using ICT & IoT and AI (HONET-ICT 2019), pp. 235–237, Charlotte, NC, USA, Oct. 6–9, 2019.
  43. [CSE 2019] X. Fu, J. Lu, X. Zhang, X. Yang, and I. Unwala, “Intelligent in-vehicle safety and security monitoring system with face recognition,” 2019 IEEE International Conference on Computational Science and Engineering (CSE 2019), pp. 225–229, New York, NY, USA, Dec. 05, 2019.
  44. [Dual 2019] Isaac Westby and X. Yang, “Real-time Digit Recognition with Neural Network on a Video Processing FPGA Platform,” 2018 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Nov. 15, 2019.
  45. [CSCI 2018] A. Gajjar, X. Yang, et al., “Mesh-IoT Based System For Large-Scale Environment,” 5th Annual Conference on Computational Science & Computational Intelligence (CSCI 2018), pp. 1019–1023, Las Vegas, NV, USA, 2018.
  46. [CSCI 2018] J. Gopaluni, I. Unwala, J. Lu, and X. Yang, “Implementation of GUI for OpenThread,” 5th Annual Conference on Computational Science & Computational Intelligence (CSCI 2018), pp. 1015–1018, Las Vegas, NV, USA, 2018.
  47. [ICACS 2018] A. Gajjar, X. Yang, et al., “An FPGA Synthesis of Face Detection Algorithm using HAAR Classifiers,” International Conference on Algorithms, Computing and Systems (ICACS 2018), pp. 133–137, Beijing, China, July 2018.
  48. [ICACS 2018] Y. Zhang, X. Yang, et al., “Exploring Slice-Energy Saving on An Video Processing FPGA Platform with Approximate Computing,” International Conference on Algorithms, Computing and Systems (ICACS 2018), pp. 138–143, Beijing, China, July 2018.
  49. [ITNG 2018] H. He, L. Wu, X. Yang, et al., “Dual Long Short-Term Memory Networks for Sub-Character Representation Learning,” The 15th International Conference on Information Technology - New Generations (ITNG 2018), Springer Advances in Intelligent Systems & Computing Book Series, Springer-Verlag, Las Vegas, NV, USA, 2018.
  50. [Dual 2018] X. Yang, “A Scalable Image/Video Processing Platform with FPGA Design and Verification Environment,” 2018 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Nov. 3, 2018.
  51. [Dual 2018] A. Gajjar and X. Yang, “Mesh-IoT Based Smart and Secure System for Wide-Range Territory,” 2018 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Nov. 3, 2018.
  52. [DASC 2017] L. Nwosu, H. Wang, J. Lu, I. Unwala, X. Yang, et al., “Deep Convolutional Neural Network for Facial Expression Recognition Using Facial Parts,” 2017 IEEE 15th International Conference on Dependable, Autonomic and Secure Computing (DASC 2017, Best Poster Award), pp. 1318–1321, Orlando, FL, USA, 2017.
  53. [ASP-DAC 2017] X. Yang and W. Wen, “Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs),” The 22nd Asia and South Pacific Design Automation Conference (ASP-DAC 2017, Regular Paper, Acceptance Rate: 31%), pp. 506–511, Chiba, Japan, Jan. 2017. Paper
  54. [SEC 2017] X. Yang and X. He, “Establishing a BLE Mesh Network using Fabricated CSRmesh Devices,” The 2nd ACM/IEEE Symposium on Edge Computing (SEC 2017, Acceptance Rate: 40%), No. 34, San Jose/Fremont, CA, USA, 2017. Paper
  55. [AHFE 2017] X. Yang and N. Wu, “Design of A Bio-Feedback Digital System (BFS) Using 33-Step Training Table for Cardio Equipment,” The 8th International Conference on Applied Human Factors and Ergonomics (AHFE 2017), pp. 53–64, Los Angeles, CA, USA, 2017.
  56. [ICAC 2017] X. Yang, Y. Zhang, W. Wen, and M. Fan, “A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration,” IEEE International Conference on Autonomic Computing (ICAC 2017) – Workshop on Feedback Computing, Columbus, OH, USA, 2017.
  57. [FYEE 2017] N. Wu, K. Zeng, J. Weidenfeller, and X. Yang, “Flipping the Classroom for Enhancing Learning and Designing in an Embedded Systems Class,” The 1st Year Engineering Experience Conference (FYEE 2017), pp. 1–4, Daytona Beach, FL, USA, 2017.
  58. [ICI 2017] D. Wu, N. Wu, K. Zeng, and X. Yang, “Recognizing Unconstrained Handwritten Digit Based on Shape Analysis and Multi-class SVM Classification,” The 8th International Conference on Information (ICI 2017), Tokyo, Japan, May 2017.
  59. [SEC 2017] A. Gajjar, Y. Zhang, and X. Yang, “A Smart Building System Integrated with An Edge Computing Algorithm and IoT Mesh Networks,” The Second ACM/IEEE Symposium on Edge Computing (SEC 2017, Acceptance Rate: 40%), Article No. 35, San Jose/Fremont, CA, USA, 2017. Paper)
  60. [Dual 2017] Y. Zhang and X. Yang, “A Novel Fog Computing Acceleration Method: Approximate FPGA Design on Adder and Multiplier,” 2017 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Oct. 28, 2017.
  61. [Dual 2017] A. Gajjar and X. Yang, “A Wide Area IoT Mesh Network With Edge Computing,” 2017 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Oct. 28, 2017.
  62. [Dual 2017] X. Yang, “A Prototype in Fog Computing (FC): Design of An FPGA-CSRmesh (FC) Platform Toward Wide-Area and Low-Energy IoT Networks,” 2017 IEEE Innovation and Automation Conference, Gilruth Recreation Center, NASA-JSA, Houston, Oct. 28, 2017.
  63. [ICI 2017] D. Wu, N. Wu, K. Zeng, and X. Yang, “Recognizing Unconstrained Handwritten Digit Based on Shape Analysis and Multi-class SVM Classification,” The 8th International Conference on Information (ICI 2017), Tokyo, Japan, May 2017.
  64. [DAC 2016] X. Yang and J. Andrian, “A Configurable and Synthesizable On-Chip Bus Architecture for Integrating Industrial Standard IPs,” 2016 Design Automation Conference (DAC 2016), WIP, Austin, TX, USA, June 2016.
  65. [ISVLSI 2014] X. Yang and J. Andrian, “A Low-Cost and High-Performance Embedded System Architecture and An Evaluation Methodology,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2014, Best Ph.D Forum Paper Award), pp. 240–243, Tampa, FL, USA, 2014. Paper
  66. [SSST 2013] X. Yang, X. Niu, and J. Fan, “Mixed-Signal System-on-Chip (SoC) Verification Based on System Verilog Model,” The 45th Southeastern Symposium on System Theory (SSST 2013), pp. 17–21, Waco, TX, USA, 2013. Paper

Abstracts/Posters, Presentations, and Invited Talks

  1. [TQS 2026] Xiaokun Yang, Yunhe Feng, Xuechen Zhang, Shui Xu, and Vipin Chaudhary, “Scalable Quantum Circuit Simulation and Accelerator,” Texas Quantum Summit, UT Dallas, Aug. 12-14, 2026.
  2. [ASCR PI Meeting 2026] Daman Rouson and Xiaokun Yang, “Towards a Verifiable Domain-Specific Language for Hardware-Accelerated Stencils”, ASCR PI meeting, July 26, 2026
  3. [NSF REU Poster 2026] Krishna Patel, Sumera Anjum, Spencer Buchanan, Xuechen Zhang, Yunhe Feng, and Xiaokun Yang, “LLM-Driven Hardware Design for Quantum Simulation Acceleration”, Poster, ENCS Undergraduate Research Showcase, Vancouver, WA, August 14, 2025.
  4. [NSF REU Poster 2026] Spencer Buchanan, Mario Vega, Doru Thom Popovici, John Shalf, and Xiaokun Yang, Poster, ENCS Undergraduate Research Showcase, August 14, 2025.
  5. [QCUF 2026] Xiaokun Yang, Xinpeng Li, Jeremy W. Turner, Cameron D. Disomma, Yunhe Feng, Xuechen Zhang, Vipin Chaudhary, and Shui Xu, “Scalable Quantum Circuit Simulation via Circuit Cutting and Hardware Acceleration,” Oak Ridge National Laboratory, Knoxville, July 20-24, 2026.
  6. [Quantum 2026] Xiaokun Yang, “Beyond Moore’s Law: Specialized Hardware Design Generation for Quantum Circuit Simulation and Verification,” Invited Talk, Quantum Workshop, UT Dallas.
  7. [SC 2025] Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, and John Shalf, “An Approach to Identify Divergences in Hardware Designs for HPC Workloads,” 11th International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC 2025), St. Louis, MO, November 21, 2025.
  8. [NSF REU Seminar 2025] X. Yang, “Specialized Hardware Design on Linear Algebra for Applications in Scientific Computing, ML, and Quantum Circuit Emulation,” UHCL Seminar, Vancouver, WA, July 24, 2025.
  9. [NSF REU Poster 2025] Jeremy Turner and Xiaokun Yang, “Hardware Generation and Acceleration for Quantum Gate Simulation,” Poster, ENCS Undergraduate Research Showcase, Vancouver, WA, August 14, 2025.
  10. [NSF REU Poster 2025] Jose Ramos and Xiaokun Yang, “Code Generation for AdderNet Neural Network,” Poster, ENCS Undergraduate Research Showcase, August 14, 2025.
  11. [UHCL Physics & Mechanical Seminar 2025] X. Yang, “DFT Beyond Moore’s Law: Hardware Acceleration for Future HPC,” UHCL Seminar, February 25, 2025.
  12. [LBL Fellowship Poster 2024] Blair Reasoner, Xiaokun Yang, Doru Thom Adrian Popovici, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Mario Vega, and John Shalf, “DFT Beyond Moore’s Law: Extreme Hardware Specialization for the Future of HPC,” Poster, Lawrence Berkeley National Laboratory, 2024.
  13. [NSF REU Poster 2024] Keaton Khoury, Blair Reasoner, Paul Wong, and Xiaokun Yang, “Design and Verification of Submodules for Density Functional Theory (DFT) Hardware Accelerator,” Poster, Undergraduate Research Showcase, Vancouver, WA, July 30, 2024.
  14. [NSF REU Poster 2024] Paul Wong and Xiaokun Yang, “Trigonometric Functions in the Chisel Hardware Construction Language,” Poster, Undergraduate Research Showcase, Vancouver, WA, July 30, 2024.
  15. [NSF REU Seminar 2024] X. Yang, “Beyond Moore’s Law: Hardware Acceleration for Future HPC and ML,” NSF REU Seminar, July 12, 2024.
  16. [LBL Fellowship Poster 2023] Blair Reasoner, Xiaokun Yang, Doru Thom Adrian Popovici, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Mario Vega, and John Shalf, “Parameterized Hardware Accelerator Design on Tall-Skinny QR Factorization,” Poster, Lawrence Berkeley National Laboratory, 2024.
  17. [SRP 2023] X. Yang, “Specialized Hardware Design on DFT for HPC,” DOE SRP, January 9–13, 2023.
  18. [LBL 2022] X. Yang, “DFT Beyond Moore’s Law: FPGA Design Specialization for HPC,” LBL Monthly Conference, November 2, 2022.
  19. [DOE VFP 2022] X. Yang, Mario Vega, Doru Thom Adrian Popovici, Nirmalendu Patra, and John Shalf, “DFT Beyond Moore’s Law: FPGA Design Specialization for 3D FFT for HPC,” DOE Visiting Faculty Program Summer Oral Presentation, August 5, 2022.
  20. [WDE 2022] Mario Vega, X. Yang, Doru Thom Adrian Popovici, Nirmalendu Patra, and John Shalf, “DFT Beyond Moore’s Law: Hardware Design Specialization for Streaming and Mixed FFTs,” WDE Poster Presentation, July 22, 2022.
  21. [CFD 2022] X. Yang, “Project-Centric Learning with OpenIC,” Faculty Development Week, Center for Faculty Development, UHCL, January 27, 2022.
  22. [SRP 2022] X. Yang, “High-Performance SoC Architecture,” DOE SRP, December 9–13, 2021.
  23. [GCC 2021] X. Yang, “FPGA Designs and Acceleration for Neural Networks,” Invited Short Talk, GCC Translational Imaging Conference, Virtual Event, November 2, 2021.
  24. [ES 2021] X. Yang, “FPGA Acceleration on Artificial Intelligence,” Invited Talk, Engineering Science Department, Sonoma State University, CA, 2021.
  25. [VRISE 2021] X. Yang, “An Implementation of Low-Cost System-on-Chip with Neural Network for Surveillance Cameras,” TC17–VRISE 2021, Virtual Event, October 8, 2021.
  26. [ICAMSE 2019] X. Yang, “An Advanced SoC Architecture for Low-Cost and Low-Power Edge Devices,” International Conference on Advanced Materials Sciences and Engineering, Osaka, Japan, 2019.
  27. [Robotics 2018] X. Yang, Y. Zhang, A. Gajjar, H. Schmoyer, and N. Ly, “Learning-on-Chip: Facial Detection with Approximations of FPGA Computing,” Robotics & AI Day, UHCL, August 3, 2018.
  28. [Robotics 2017] Y. Zhang and X. Yang, “Exploring Approximate Designs for FPGA-Based Edge Computing,” Robotics & AI Day, UHCL, July 21, 2017.
  29. [Robotics 2017] A. Gajjar and X. Yang, “A Smart Building System Integrated with an Edge Computing Algorithm and IoT Mesh Networks,” Robotics & AI Day, UHCL, July 21, 2017.
  30. [GBS 2016] X. Yang, “A High-Performance AES-Encrypted On-Chip Bus Architecture for Internet-of-Things System-on-Chips,” IEEE Galveston Session, NASA Johnson Space Center, Gilruth Recreation Center, November 17, 2016.