A Quantum-Classical Co-Design Framework for Scalable Quantum Circuit Simulation and Acceleration
As Moore’s Law continues to plateau, the industry has increasingly turned to specialized hardware design solutions to sustain performance scaling, particularly for artificial intelligence and high-performance computing applications. Representative examples of this paradigm shift include Google’s Tensor Processing Units (TPUs); Amazon AWS’s Graviton, Trainium, and Inferentia processors; Apple’s A- and M-series system-on-chips (SoCs); Meta’s Training and Inference Accelerator (MTIA); Microsoft’s Maia and Cobalt chips; Tesla’s Dojo accelerators; Broadcom’s custom AI application-specific integrated circuits (ASICs); and large-scale FPGA-based systems. Building on this trend, this project introduces a transformative quantum–classical co-design framework that tightly integrates circuit-cutting techniques with specialized multi-FPGA architectures to enable scalable and accelerated simulation.